The present invention generally relates to a semiconductor device having a trench for use in isolation or capacitor formation and a method for producing the same, and in particular to a semiconductor device having an isolation-merged vertical capacitor cell, and a method for producing the same. More particularly, the present invention relates to a dynamic random access memory device having an improvement by which it becomes possible to prevent a leakage current due to the presence of a parasitic metal-oxide-semiconductor field effect transistor (MOSFET) formed in the memory device.
A dynamic random access memory (hereafter simply referred to as a DRAM) is classified into two types: one of which is a stacked type DRAM, and the other is an isolation-merged vertical capacitor cell type DRAM. Recently, as the integration density increases, there has been increased activity in the development of an isolation-merged vertical capacitor (hereafter simply referred to as an IVEC) cell type DRAM. In IVEC cell type DRAMs, a trench isolation is used for electrically isolating elements from each other, and a trench capacitor is used for storing a charge in a memory cell. The trench capacitor is formed so as to be buried in the trench. With this structure, it becomes possible to reduce the capacitor area and therefore the cell area.
It is known that conventional IVEC cell type DRAMs have a problem in which a parasitic MOS transistor is formed along a sidewall of a transistor region which is formed around trench isolations and has source and drain regions. This is also called a parasitic sidewall MOSFET. The parasitic MOS transistor causes a leakage current to pass through a sidewall portion of a channel formed in the transistor region. Such a sidewall portion of the channel is also called a parasitic sidewall channel. The above-mentioned problems have been reported in the following two papers: (1) S. Nakajima, et al., "AN ISOLATION-MERGED VERTICAL CAPACITOR CELL FOR LARGE CAPACITOR DRAM", IEDM Tech. Dig., 1984, pp. 240-243; (2) T. Morie et al., "ELECTRICAL CHARACTERISTICS OF ISOLATION-MERGED VERTICAL CAPACITOR (IVEC) CELL", 1985 Symposium on VLSI Technology, May 1985, pp. 88-89.
These papers disclose that to prevent the leakage current from passing through the parasitic sidewall channel, parasitic sidewall MOSFET gate oxide thickness, transfer MOSFET gate oxide thickness and channel impurity concentration are optimized. However, the above-mentioned proposal cannot greatly reduce the leakage current. It is noted that the papers disclose a storage electrode of the IVEC formed around the transistor region. This arrangement of the storage electrode increases capacitance of the IVEC. However, a large amount of leakage current may be induced.